`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
//detect 01110001
localparam IDLE=8'b00000000;
localparam S1=8'b00000001;
localparam S2=8'b00000010;
localparam S3=8'b00000100;
localparam S4=8'b00001000;
localparam S5=8'b00010000;
localparam S6=8'b00100000;
localparam S7=8'b01000000;
localparam S8=8'b10000000;

reg [7:0]state;
reg [7:0]next_state;

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		state<=IDLE;
	end
	else begin
		state<=next_state;
	end
end
always@(*)begin
	case(state)
		IDLE:begin
			//match=1'b0;
			next_state=(a==0)?S1:IDLE;
		end
		S1:begin
			//match=1'b0;
			next_state=(a==1)?S2:S1;
		end
		S2:begin
			//match=1'b0;
			next_state=(a==1)?S3:S1;
		end
		S3:begin
			//match=1'b0;
			next_state=(a==1)?S4:S1;
		end
		S4:begin
			//match=1'b0;
			next_state=(a==0)?S5:IDLE;
		end
		S5:begin
			//match=1'b0;
			next_state=(a==0)?S6:S2;
		end
		S6:begin
			//match=1'b0;
			next_state=(a==0)?S7:S2;
		end
		S7:begin
			//match=1'b0;
			next_state=(a==1)?S8:S1;
		end
		S8:begin
			//match=1'b1;
			next_state=(a==0)?S1:S3;
		end
		default:begin
			//match=1'b0;
			next_state=IDLE;
		end
	endcase
end
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        match<=1'b0;
    end
    else begin
        match<=state==S8;
    end
end

endmodule